1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device including a redundancy circuit.
2. Description of the Background Art
A semiconductor memory device including a redundancy circuit is developed for improving the yield of semiconductor memory devices. The usage of a redundancy circuit allows a word line to be replaced with a redundant word line when that certain word line or a memory cell connected to that certain word line is defective. Thus, defective word lines or memory cells can be repaired.
FIG. 4 is a block diagram showing a structure of the main components of a conventional semiconductor memory device including a redundancy circuit.
A memory cell array 1 includes a plurality of word lines WL, a plurality of bit line pairs BL crossing the plurality of word lines WL, and a plurality of memory cells MC provided at the crossings thereof. This memory cell array 1 further includes a redundant word line RWL, and a plurality of memory cells MC connected thereto.
A decoder 2 and a sense amplifier unit 13 are connected to memory cell array 1. Sense amplifier unit 13 includes a plurality of sense amplifiers and transfer gates connected to the plurality of bit line pairs BL, and a decoder.
The present semiconductor memory device includes a replacement circuit 10. Replacement circuit 10 includes a redundancy select circuit 3, a replacement address program circuit 4, and an NAND circuit 5. Replacement circuit 10 and a redundant word line RWL form a redundancy circuit.
The operation of the semiconductor memory device of FIG. 4 will be described hereinafter.
Decoder 2 responds to an X address XA to select one of the plurality of word lines WL in memory cell array 1 to pull up the potential of the selected word line WL to an H level (logical high). This causes data to be read out to a corresponding bit line pair BL from a memory cell MC connected to the selected word line WL. These data are amplified by a sense amplifier included in sense amplifier unit 13. The decoder in sense amplifier unit 13 responds to a Y address signal YA to render one of the plurality of transfer gates conductive. As a result, one data is output.
When there is a fault concerning a certain word line WL, a redundant word line RWL is used as a substitute for that word line WL. In this case, the output of redundancy select circuit 3 attains an H level. Also, the address of a word line WL to be replaced is programmed in replacement address program circuit 4.
When the address specified by X address signal XA matches the address (replacement address) programmed in replacement address program circuit 4, the output of replacement address program circuit 4 attains an H level. When the outputs of redundancy select circuit 3 and replacement address program circuit 4 attain an H level, the output of NAND circuit 5 (data inactive signal DA) is pulled down to an L level (logical low). This renders the decoder inactive, whereby all the word lines WL attain a de-selected state. The potential of redundant word line RWL is pulled up to an H level.
Thus, when a defective word line WL or a word line WL connected to a defective memory cell MC is selected, a redundant word line RWL is selected instead of that word line WL.
Although memory cell array 1 may include a redundant bit line pair, such a redundant bit line pair is omitted in FIG. 4.
FIG. 5 is a circuit diagram showing a detailed structure of redundancy select circuit 3. Redundancy select circuit 3 includes a fuse 31, an MOS capacitor 32, a high resistor 33, P channel transistors 34, 35, and an N channel transistor 36.
In a normal mode, i.e. when a redundant word line RWL is not used (redundancy de-selected), fuse 31 attains a connected state. Therefore, the potential of a node N1 attains a ground level, so that a signal of an L level enters NAND circuit 5 of FIG. 4. As a result, data inactive signal DA attains an H level, so that the potential of redundant word line RWL is not pulled up.
When redundant word line RWL is used (redundancy selected), fuse 31 is disconnected. When power is turned on, the potential of node N1 rises to an H level by the current flowing in high resistor 33 when the increasing level of the power supply voltage is moderate. When the increasing level of the powers supply voltage is abrupt, the potential of node N1 rises towards an H level by the capacitive coupling of MOS capacitor 32. Furthermore, the potential of node N1 arrives at a complete H level by the positive feedback circuit formed of transistors 34, 35 and 36.
Thus, the output of redundancy select circuit 3 attains an L level and an H level when redundancy is de-selected and selected, respectively.
FIG. 6 is a circuit diagram showing a detailed structure of replacement address program circuit 4. An address setting circuit 40 includes a fuse 41, an MOS capacitor 42, a high resistor 43, P channel transistors 44, 45, and an N channel transistor 46. An address setting circuit 50 includes a fuse 51, an MOS capacitor 52, a high resistor 53, P channel transistors 54, 55, and an N channel transistor 56. The structure and operation of address setting circuits 40 and 50 are similar to those of the redundancy select circuit 3 shown in FIG. 5.
Therefore, the potential of node N3 of address setting circuit 4 attains an L level and an H level when fuse 41 is connected and disconnected, respectively. Similarly, the potential of node N5 of address setting circuit 50 attains an L level and an H level when fuse 51 is connected and disconnected, respectively.
P channel transistors 61 and 62 and N channel transistors 71 and 72 are connected between an input terminal I1 and an output terminal O1. P channel transistors 63 and 64 and N channel transistors 73 and 74 are connected between an input terminal I2 and an output terminal O1. P channel transistors 65 and 66 and N channel transistors 75 and 76 are connected between an input terminal I3 and output terminal O1. P channel transistors 67 and 68 and N channel transistors 77 and 78 are connected between an input terminal I4 and output terminal O1.
The gate electrodes of transistors 61, 73, 65 and 77 are connected to a node N3 in address setting circuit 40. The gate electrodes of transistors 71, 63, 75 and 67 are connected to a node N4 of address setting circuit 40. The gate electrodes of transistors 62, 64, 76 and 78 are connected to a node N5 of address setting circuit 50. The gate electrodes of transistors 72, 74 and 66 and 68 are connected to a node N6 of address setting circuit 50.
A predecode signal which is a predecoded version of X address signal XA is programmed in replacement address program circuit 4 of FIG. 6. The programming method in program circuit 4 will be described hereinafter.
First, predecode signals X0.multidot.X1, X0.multidot./X1, /X0.multidot.X1, and /X0.multidot./X1 are defined as follows:
When X0=H level and X1=H level, X0.multidot.X1=H level PA1 When X0=H level and X1=L level, X0.multidot./X1=H level PA1 When X0=L level and X1=H level, /X0.multidot.X1=H level PA1 When X0=L level and X1=L level, /X0.multidot./X1=H level
Otherwise, each of predecode signals X0.multidot.X1, X0.multidot./X1, /X0.multidot.X1, and /X0.multidot./X1 attains an L level.
Here, predecode signal X0.multidot.X1 is applied to input terminal I1. predecode signal X0.multidot./X1 is applied to input terminal I2, predecode signal /X0.multidot.X1 is applied to input terminal I3, and predecode decode signal /X0.multidot./X1 is applied to input terminal I4.
When fuses 41 and 51 are connected, only input terminal I1 is connected to output terminal O1. As a result, predecode signal X0.multidot.X1 appears at output terminal O1. Therefore, when X0=H level and X1=H level, the output attains an H level. Since redundant word line RWL is selected here, an address of X0=X1=H level is programmed in replacement address program circuit 4 by fuses 41 and 51.
Similarly, X0.multidot./X1 appears at output terminal O1 when fuse 41 is disconnected and fuse 51 is connected. Therefore, an address of X0=H level, X1=L level is programmed. When fuse 41 is connected and fuse 51 is disconnected, /X0.multidot.X1 appears at output terminal O1. Therefore, an address of X0=L level, X1=H level is programmed. When fuses 41 and 51 are disconnected, X0.multidot./X1 appears at output terminal O1. Therefore, an address of X0=X1=L level is programmed.
In replacement address program circuit 4 of FIG. 6, four predecode signals X0.multidot.X1, X0.multidot./X1, /X0.multidot.X1, and /X0.multidot./X1 which are two X address signals X0 and X1 predecoded are applied. There are generally more than four X address signals. Therefore, a plurality of the circuits shown in FIG. 6 are provided, wherein the output of each circuit is applied to NAND circuit 5 shown in FIG. 4.
When memory cell arrayl is divided into a plurality of memory blocks, a redundant word line RWL is provided in each memory block. If only one replacement circuit 10 of FIG. 4 is provided, only one defect can be repaired even though there are a plurality of redundant word lines RWL corresponding to the number of memory blocks.
U.S. Pat. No. 5,392,247 discloses a semiconductor memory device including a replacement circuit for each memory block to solve such a problem.
FIG. 7 is a block diagram showing a structure of four replacement address program circuits 4a-4d in four replacement circuits 10 provided for every memory block.
When there is no defect, it is not necessary to program a replacement address in any of the four replacement address program circuits 4a-4d shown in FIG. 7. Therefore, fuses 41 and 51 in address setting circuits 40 and 50 are not disconnected. As a result, transistors 61, 62, 71 and 72 in all the replacement address program circuits 4a-4d attain a conductive state, whereby predecode signal X0.multidot.X1 applied to input terminal I1 will always appear at respective output terminals O1a-O1d.
This means that, when a redundant word line RWL is not used, only one predecode signal X0.multidot.X1 out of the four predecode signals must charge the negative capacitance of the four output terminals O1a-O1d. Therefore, the load to be driven by a particular predecode signal X0.multidot.X1 becomes larger as the number of replacement circuits 10 increases. As a result, there is a great difference between the load of a certain predecode signal X0.multidot.X1 and that of another predecode signal. Thus, there was a problem that only the rising time or falling time of a predecode signal X0.multidot.X1 is increased.